1. Field of the Invention
The present invention relates generally to integrated circuit chip package technology and, more particularly, to a reduced size stacked semiconductor package and method of making the same.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die attach pad or die pad of the leadframe also remains exposed within the package body. In other semiconductor packages, the metal leadframe is substituted with a laminate substrate to which the semiconductor die is mounted and which includes pads or terminals for mimicking the functionality of the leads and establishing electrical communication with another device.
Once the semiconductor dies have been produced and encapsulated in the semiconductor packages described above, they may be used in a wide variety of electronic devices. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically includes a printed circuit board on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor dies highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
Even though semiconductor packages have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a need to find a semiconductor package design to maximize the number of semiconductor packages that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor packages. One method to minimize space needed to accommodate the semiconductor packages is to stack the semiconductor packages, individual semiconductor dies, or other devices on top of each other, or to stack the semiconductor dies or other devices within the package body of a semiconductor package. However, when attempting to integrate more than two or three devices such as memory chips into a vertical stack, test yield loss typically becomes higher as more such devices are assembled in a single package.
Additionally, many existing stacked packages include a substrate which is larger than the stacked semiconductor dies included in the package. As a result of the typical encapsulation of the semiconductor dies in such packages by an encapsulant material, the size of such packages is usually considerably larger than that of the semiconductor dies included therein, thus creating difficulties in realizing a true chip scale package. Moreover, for widely used stacked combinations such as a memory/memory combination, a memory/logic combination, a memory/ASIC combination, or a flash/SRAM combination, such a combination of devices generally reduces the number of input/output or I/O. For example, in a flash/SRAM combination which is widely used in cellular phones, it is only possible to share about 50% of the I/O. The I/O is collected to the substrate of the package and then routed by a PCB, with the two semiconductor dies thus sharing the I/O. Still further, since stacked packages often employ the use of gold wires, solder bumps, substrates and the like to achieve prescribes patterns of electrical signal routing, these particular features often give rise to problems such as cross torque which create difficulties in using such packages in high frequency regions. Therefore, a new solution is needed, such solution being provided by the present invention which is discussed in detail below.